In the field of semiconductor integrated circuits, particularly where silicon is the primary semiconductor, the use of non-monocrystalline silicon has become widespread. For example, doped polycrystalline silicon is widely used as a gate material for metal-oxide-semiconductor (MOS) transistors, as its work function facilitates the fabrication of high performance enhancement mode transistors. In addition, the conductivity of doped polycrystalline silicon is sufficiently high that it can be used as interconnection material in integrated circuits.
Polycrystalline silicon (commonly referred to as polysilicon) film is generally formed by chemical vapor deposition, usually by the decomposition of silane (SiH.sub.4) gas at low pressure. A conventional method of forming a film of doped polysilicon is to deposit an undoped polysilicon film, and then dope the deposited film by diffusion or ion implantation. A common method of n-type diffusion doping is the decomposition of POCl.sub.3 in a CVD reactor, so that phosphorous is deposited over the undoped polysilicon film, followed by a high temperature anneal (commonly performed at 850.degree. C. or 900.degree. C., for twenty to thirty minutes) to diffuse the deposited phosphorous into the film. The polysilicon film can also be doped by ion implantation of boron (for p-type), or arsenic or phosphorous (for n-type), also followed by a high temperature anneal to diffuse the implanted dopant into the film.
The above-described method of depositing undoped polysilicon and thereafter doping the film has been widely used in the industry. This method not only requires the additional steps of deposition or ion implantation, and in both cases a high temperature anneal, but also is not readily compatible with the processing requirements of many modern integrated circuits. For example, the use of silicide-clad junctions has become more common in recent years. An example of a method for the direct reaction of a refractory metal with silicon to form a silicide-clad junction is described in U.S. Pat. No. 4,545,116 issued Oct. 8, 1985, assigned to Texas Instruments Incorporated, and incorporated herein by this reference. Once the silicide is in place over a doped region of the substrate, however, the temperature to which the structure is subsequently subjected, as well as the time spent at such a temperature, must be limited, as the high temperature can cause remaining atoms of the refractory metal to react with the underlying silicon. In modern integrated circuits where the junction depth is required to be quite shallow (e.g., below 0.2 micron), such additional high temperature exposure could cause the doped region to be totally consumed by the silicide at a location, shorting out the junction. In some structures, for example a BiCMOS structure having a doped polysilicon emitter electrode, a doped polysilicon film may be formed after the silicide cladding of the MOS source/drain junctions. In such a structure, the method of subsequently doping an undoped polysilicon film may not be desirable.
A second technique known in the industry for forming a doped polysilicon film is commonly referred to as in-situ doping. This is accomplished by the introduction of dopant gas during the chemical vapor deposition of the polysilicon, so that the resultant polysilicon film contains dopant throughout, without requiring subsequent doping and annealing steps. For n-type dopant, a common dopant gas is phosphine (PH.sub.3); the phosphine is conventionally mixed with the silane gas prior to its introduction into the CVD reactor. However, the use of phosphine as the source gas provides multiple problems Phosphine gas is quite toxic, and accordingly thorough handling precautions and equipment are required for its use. In addition, phosphine can "poison" the surface of the wafer upon which the deposition is taking place, which not only slows the deposition rate, but also results in non-uniform polysilicon film thickness over the surface of the wafer, and also from wafer to wafer when deposition occurs in a multiple-wafer chamber. Such problems are described by B. Meyerson et al., in "Phosphorous-Doped Polysilicon via LPCVD", J. Electrochem. Soc. 129, 1984, p. 2361. While the uniformity problems may be addressed by specially designing the LPCVD furnaces, using caged boats and wider wafer spacing (see A. Learn et al., "Deposition and Electrical Properties of In-situ Phosphorous Doped Silicon Films Formed by LPCVD," J. Appl. Phys. 61(5), p. 1898, 1987), such equipment-based solutions can introduce particle contaminants, and are incompatible with higher-level automation and with mass production high volume wafer fabrication factories.
In addition, many integrated circuits are now using polysilicon to fill trenches etched into the substrate. Such filled trenches can be used for isolation purposes, as described in U.S. Pat. No. 4,631,803, issued Dec. 30, 1986, and in U.S. Pat. No. 4,835,115, issued May 30, 1989, both assigned to Texas Instruments Incorporated and incorporated herein by this reference, or for purposes of making connection to underlying layers in the substrate, as described in copending application Ser. No. 178,728, filed Apr. 7, 1988, assigned to Texas Instruments Incorporated and also incorporated herein by this reference. Another important use of a polysilicon filled trench is a memory cell in a dynamic random access memory (dRAM), where a storage capacitor is formed in a trench etched into the substrate. In the example of a dRAM, the storage capacitor is formed having opposing plates of the sides of the trench and a doped polysilicon plug filling the trench, and separated from the walls of the trench by a thin dielectric. Examples of trench capacitor dRAM cells are shown in copending application Ser. No. 385,340, Ser. No. 385,341, Ser. No. 385,601, and Ser. No. 385,328, all filed Jul. 25, 1989, all assigned to Texas Instruments Incorporated, and all incorporated herein by this reference. In addition, devices having vertical transistors can utilize polysilicon gate electrodes disposed within a trench. Examples of such a device, not only having a vertical transistor but also having having the storage capacitor disposed within a trench, and accordingly utilizing multiple polysilicon plugs within the trench, are described in U.S. Pat. No. 4,830,978, issued May 16, 1989, assigned to Texas Instruments Incorporated, and incorporated herein by this reference.
Due to the depth of the trenches in these structures, and accordingly the depth of the doped polysilicon plug, the method of depositing an undoped polysilicon film and subsequently doping it (either by diffusion or ion implantation) has limited use in the application of polysilicon-filled trenches. Accordingly, in-situ doping of the polysilicon plugs is much preferred for these applications. In order to successfully fill the trench with deposited polysilicon, however, the deposited film must have a high degree of conformality over the surface of the wafer, and into the trench When phosphine has been used as the in-situ dopant for a polysilicon plug, it has been observed that the conformality is poor (see K. Sawada et al., "Formation of Polysilicon Electrodes in Deep Trenches with Two-step Continuous Deposition of In-situ Doped and Undoped Polysilicon Films", Symposium on VLSI Technology (1989), p. 41). As modern high density dRAMs, such as 16 Mbit dRAMs, may include high-aspect ratio trenches (e.g., 12 microns deep and 1 micron across), conformal in-situ doped polysilicon is a stringent requirement.
U.S. Pat. No. 4,877,753, issued Oct. 31, 1989, assigned to Texas Instruments Incorporated, and incorporated herein by this reference, describes a method for in-situ doping a polysilicon film using phosphorous sources other than gaseous phosphine, including tertiary butyl phosphine. As described in this patent, these dopant sources provide the advantage of lower toxicity, as compared with phosphine gas, as well as provide films with improved thickness uniformity and lower sheet resistance.
It is an object of this invention to provide a method of forming in-situ doped silicon films with further improvements in thickness uniformity, while providing a film with low sheet resistance at a reasonable deposition rate.
It is a further object of this invention to provide such a method which has improved conformality, and is therefore especially advantageous in forming silicon plugs for trenches.
It is a further object of this invention to provide such a method which can be done at relatively low temperatures while still maintaining good uniformity and sheet resistance values, at a reasonable deposition rate, in such a manner as to be compatible with modern high-density fabrication processes.
It is a further object of this invention to provide an apparatus which is especially adapted to depositing an in-situ doped silicon film with the above properties.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to this specification together with the drawings.